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<div class="header">
  <div class="headertitle"><div class="title">PWR_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Power Control.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:a50f96f92968bc5b9b40b870531dde182" id="r_a50f96f92968bc5b9b40b870531dde182"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a50f96f92968bc5b9b40b870531dde182">CR1</a></td></tr>
<tr class="memitem:a682b6c3f4af70d7faf280b2e65b3d4a4" id="r_a682b6c3f4af70d7faf280b2e65b3d4a4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a682b6c3f4af70d7faf280b2e65b3d4a4">CSR1</a></td></tr>
<tr class="memitem:a8426bae04fc4cae7425f07c50f2359ec" id="r_a8426bae04fc4cae7425f07c50f2359ec"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a8426bae04fc4cae7425f07c50f2359ec">CR2</a></td></tr>
<tr class="memitem:a5b7c92606919491fb50de53447078fd4" id="r_a5b7c92606919491fb50de53447078fd4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a5b7c92606919491fb50de53447078fd4">CR3</a></td></tr>
<tr class="memitem:accb03e795c571cf5db2c3827ab7329b4" id="r_accb03e795c571cf5db2c3827ab7329b4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#accb03e795c571cf5db2c3827ab7329b4">CPUCR</a></td></tr>
<tr class="memitem:a0af78d1aac1a6f0793f6cef9f2695cdb" id="r_a0af78d1aac1a6f0793f6cef9f2695cdb"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0af78d1aac1a6f0793f6cef9f2695cdb">RESERVED0</a></td></tr>
<tr class="memitem:af60b520f33b6acfffd301d205f487cef" id="r_af60b520f33b6acfffd301d205f487cef"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af60b520f33b6acfffd301d205f487cef">D3CR</a></td></tr>
<tr class="memitem:ace3487dfe91fb691a96a76a048ccb887" id="r_ace3487dfe91fb691a96a76a048ccb887"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ace3487dfe91fb691a96a76a048ccb887">RESERVED1</a></td></tr>
<tr class="memitem:a2e3e128a82d90702992e10086b230e10" id="r_a2e3e128a82d90702992e10086b230e10"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2e3e128a82d90702992e10086b230e10">WKUPCR</a></td></tr>
<tr class="memitem:a73a21c4e6e9dc0fd4f119247c78963a1" id="r_a73a21c4e6e9dc0fd4f119247c78963a1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a73a21c4e6e9dc0fd4f119247c78963a1">WKUPFR</a></td></tr>
<tr class="memitem:aa4f0cbb60ffc8af7e3f90f11a6fa120a" id="r_aa4f0cbb60ffc8af7e3f90f11a6fa120a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa4f0cbb60ffc8af7e3f90f11a6fa120a">WKUPEPR</a></td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Power Control. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="accb03e795c571cf5db2c3827ab7329b4" name="accb03e795c571cf5db2c3827ab7329b4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#accb03e795c571cf5db2c3827ab7329b4">&#9670;&#160;</a></span>CPUCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PWR_TypeDef::CPUCR</td>
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<p>PWR CPU control register, Address offset: 0x10 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a50f96f92968bc5b9b40b870531dde182">&#9670;&#160;</a></span>CR1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PWR_TypeDef::CR1</td>
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<p>PWR power control register 1, Address offset: 0x00 </p>

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<a id="a8426bae04fc4cae7425f07c50f2359ec" name="a8426bae04fc4cae7425f07c50f2359ec"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8426bae04fc4cae7425f07c50f2359ec">&#9670;&#160;</a></span>CR2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PWR_TypeDef::CR2</td>
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<p>PWR power control register 2, Address offset: 0x08 </p>

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<a id="a5b7c92606919491fb50de53447078fd4" name="a5b7c92606919491fb50de53447078fd4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5b7c92606919491fb50de53447078fd4">&#9670;&#160;</a></span>CR3</h2>

<div class="memitem">
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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PWR_TypeDef::CR3</td>
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<p>PWR power control register 3, Address offset: 0x0C </p>

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<a id="a682b6c3f4af70d7faf280b2e65b3d4a4" name="a682b6c3f4af70d7faf280b2e65b3d4a4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a682b6c3f4af70d7faf280b2e65b3d4a4">&#9670;&#160;</a></span>CSR1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PWR_TypeDef::CSR1</td>
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<p>PWR power control status register 1, Address offset: 0x04 </p>

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<a id="af60b520f33b6acfffd301d205f487cef" name="af60b520f33b6acfffd301d205f487cef"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af60b520f33b6acfffd301d205f487cef">&#9670;&#160;</a></span>D3CR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PWR_TypeDef::D3CR</td>
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<p>PWR D3 domain control register, Address offset: 0x18 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a0af78d1aac1a6f0793f6cef9f2695cdb">&#9670;&#160;</a></span>RESERVED0</h2>

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          <td class="memname">uint32_t PWR_TypeDef::RESERVED0</td>
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<p>Reserved, Address offset: 0x14 </p>

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<a id="ace3487dfe91fb691a96a76a048ccb887" name="ace3487dfe91fb691a96a76a048ccb887"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ace3487dfe91fb691a96a76a048ccb887">&#9670;&#160;</a></span>RESERVED1</h2>

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          <td class="memname">uint32_t PWR_TypeDef::RESERVED1</td>
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<p>Reserved, Address offset: 0x1C </p>

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<a id="a2e3e128a82d90702992e10086b230e10" name="a2e3e128a82d90702992e10086b230e10"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2e3e128a82d90702992e10086b230e10">&#9670;&#160;</a></span>WKUPCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PWR_TypeDef::WKUPCR</td>
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<p>PWR wakeup clear register, Address offset: 0x20 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa4f0cbb60ffc8af7e3f90f11a6fa120a">&#9670;&#160;</a></span>WKUPEPR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PWR_TypeDef::WKUPEPR</td>
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<p>PWR wakeup enable and polarity register, Address offset: 0x28 </p>

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<a id="a73a21c4e6e9dc0fd4f119247c78963a1" name="a73a21c4e6e9dc0fd4f119247c78963a1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a73a21c4e6e9dc0fd4f119247c78963a1">&#9670;&#160;</a></span>WKUPFR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PWR_TypeDef::WKUPFR</td>
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<p>PWR wakeup flag register, Address offset: 0x24 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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